603 support

[Benjamin Herrenschmidt]

>The tlbie instruction will flush kernel pages since it
>does not decode the ea completely. MOL might also zero 
>out a kernel PTE entry if a MOL PTE has been evicted 
>previously.
>
>However, taking a closer look at my 604e manual, it seems
>like tlbies should be guarded by a lock:
>
>"When a snooping 604e detects a TLB invalidate entry
>on the bus, it accepts the operation only if no TLB invalidate
>entry operation is beeing executed by this processor
>and only if all processors on the bus accepts the operation
>(ARTRY is not asserted)."
>
>The question is what happens if two processors issue tlbies 
>simultaneously? I guess the flush is either ignored
>by the other processor or ARTRY asserted which I guess
>could result in a deadlock situation since both processors 
>are executing tlbies.

Interesting. I noticed darwin has a special lock just for
tlbie's.

>> Beware also that the linux PTE will be possibly in highmem
>> on 2.5... 
>
>I haven't looked at the highmem implementation for PPC, but I 
>guess this involves these extra PTE bits the 7450 has.

No, I'm not talking about the extended address space, but what
linux calls highmem, which means that the kernel doesn't map
the entire physical memory at PAGE_OFFSET. Things like page
cache pages are mapped on demand, and on 2.5, linux PTEs as
well. 

>> But since Paulus also changed the whole exception
>> entry/exit code path (we don't save all registers any more,
>> only volatile ones, the others get saved lazily on context
>> switch), MOL will probably require some ground work for 2.5
>
>MOL no longer makes any assumptions about the kernel implementation
>of the exceptions, so this shouldn't be an issue. MOL only 
>depend upon the page table format, the kernel usage of VSIDs 
>and the page flushing hook.

Ok.