[ydl-gen] PS3 Linux and Controller

[Derick Centeno]

Hi Henry:

Thanks to the links you provided I was able to discover this one:

http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/D21E662845B95D4F872570AB0055404D

It is the "Introduction to the Cell Broadband Engine".

"The Cell Broadband Engine (CBE) contains a dual-threaded Power 
Processor Element (PPE), eight Synergistic Processor Elements (SPEs) an 
on-chip Rambus XDR controller with support for two banks of Rambus XDR 
memory and an aggregate memory bandwidth of 25.6 GB/s as well as a 
configurable I/O interface capable of (raw) bandwidth of up to 25+25GB/s 
in symmetrical configurations. ... An on-chip coherent fabric ... is 
organized as four rings two of which run clockwise and two 
counterclockwise, with a separate command fabric.  This "Element 
Interconnect Bus" is completely managed by hardware, and programmers are 
generally not aware of it.  The SPEs can simultaneously source and sink 
8 bytes per processor cycle (25.6+25.6GB/s at 3.2GHz) and deliver 8 
single precision flops per cycle (25.6GFlops at 3.2GHz per SPE and 200+ 
GFlops for CBE).  The SPEs are dual-issue processors, and can perform a 
load, store, shuffle, channel or branch operation in parallel with a 
computation.  ... with 8 processors on a single die ..."

It is fairly easy, in reviewing what IBM has published, to understand 
how anyone could present a different description of their effort.  This 
is not really a big issue as IBM's intent was merely a general 
overview.  I could be wrong but I don't believe their (or anyone else's) 
White Papers (or other public documents) are presented with the 
intention of being a succinct explanation equivalent to instructions 
available at a typical science or engineering lab at college.

What the public experiences as they acquire the PS3 with YDL 5, will be 
far more important.  No discussion or analysis either from within IBM or 
elsewhere -- can determine what the user's experience will be when it 
starts to become clear that this is not only a game computer; it is also 
a computer one can also potentially use for serious exploration and 
learning.  Maybe this can be one instance where it may be justified to 
rewrite a favorite expression within the StarTrek universe so that it 
instead is expressed as "to go where no mind has gone before"!

Best wishes...
------------------------------------------------------------------------

Henry A. Leinhos wrote:
> Derick, 
>
> I'm not sure how either of your references addresses the original comment 
> that the Cell SPEs are not SMP cores, but rather co-processors. 
>
> Looking at IBM's developer references: 
>
> http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell_Broadband_Eng 
> ine 
>
> there are several papers addressing the Cell architecture.  One 
> (2053_IBM_CellIntro.pdf) presents a good overview of the Cell.  In it it 
> refers to several programming models for the SPEs:  device extension model, 
> function offload model, and streaming programming model.  The SPEs are 
> *clearly* co-processors tightly coupled with a modified PPC 970.  The power 
> in the cell is that it provides the hardware for very efficient parallel 
> signal processing, not that it is a 9-way SMP machine (1 PPC + 8 SPEs). 
>
>
> Regards,
> Henry 
>
>   
>