[ydl-gen] Cell architecture.

[Laurent Desnogues]

On 9/15/07, Andres Tello Abrego <criptos at aullox.com> wrote:
> I have a technical question...

You will find all the gory details on IBM DW site.  For instance:

http://www.ibm.com/developerworks/power/cell/docs_hardware.html?S_TACT=105AGX16&S_CMP=HP

>  Some time ago, I have read that no all SPE from the Cell do the same.
> That there are specialized SPE, and I'm not referring to the PPE.

All the SPEs are the same.  However they are connected on a
circular ring and so communication speed depends on the
placement of your application.

On the PS3, one of the SPEs is reserved by the Hypervisor.
Also PS3 Cell only has 7 SPEs (probably due to initial yield
problems).

> I been reading and searching for this issue, on the net this, two past
> days, but I been unable to found accurate information.

Cf my link above ;)

> All I have found, talks about the EBI o BIE, well, the bus connecting
> the SPEs, Ram and so on, but the documents I have found, manage as a 7+1
>  architecture, like if all SPE are equal.
>
> Also, I'm not sure, dees SPE support Altivec?.

No the SPE has its own instruction set.  cf ISA docs on IBM site.
The SPE has many instructions that are very similar to Altivec.

> Also I have read that the SPE and the PPE execute in order instructions,
> is this true? There is no out of order execution, branch prediction? Or
> the PPE issue the instrucction to the SPE, and the SPE compute, not
> caring what kind of instruction is issued?

SPE indeed are in-order with no branch prediction (IIRC the same
applies to the PPE).

The SPEs are independent processors with their own memory.
Basically the PPE upload a program to one or several SPEs and
let them run.  Of course PPE and SPEs can communicate.

To sum up, you will find answers to all of your questions on IBM
web site :)

Hope this helps,

Laurent