AltiVec Kernel Enhancements from MOT

[Dorothy over the RGB]

> Try looking at /proc/l2cr, which will display 
> the contents of the G3/G4 L2 cache control register.

I'm getting this:

shell> sysctl -a | grep l2cr

# With MacOS Sonnet Extension OFF

kernel.l2cr = 0x00000000:  disabled, no parity, 2MB, clock disabled, 
flow-through burst SRAM, copy-back, 0.5ns hold

# With MacOS Sonnet Extension ON

kernel.l2cr = 0xb9000000:  enabled, no parity, 1MB, +2 clock, pipelined burst 
SRAM, copy-back, 0.5ns hold