L2 Cache and Processor Speed

[Andreas Tobler]

Morning,

thank you for feedback!

Blake Skinner wrote:
> Thanks! Works perfectly (that I can tell anyway). Now I just need to 
> find a way to increase the multiplier on my cache (running at 166Mhz 
> instead of 250Mhz). Also, just as a note to anyone who tries to compile 
> this, you need to:
> 
> ln -s  /usr/src/linux/arch/ppc/kernel/ppc_defs.head 
> /usr/src/linux/include/asm/ppc_defs.h
> ln -s  /usr/src/linux/arch/ppc/kernel/ppc_asm.h 
> /usr/src/linux/include/asm/ppc_asm.h

Yup, have to tune it a bit. And meake it world buildable.

Do you have this sonnet? (STIPPCG3500512)  Sonnet Crescendo/PCI 
G3/500MHz 512k 3:1(167MHz) Backside Cache

No, it can't be this one, you have 0xbd000000 as L2 value.

It is possible that you can select the L2Div in the software panel under 
OS9. Not for sure. You can also set it in Linux, but, from my experience 
this could be tricky and freeze the machine. I couldn't change my L2Div 
on my Zif G3/500 to every value I wanted. I got hard freezes.

Here my actual value, note, the last two digits are not relevant since 
they're readonly PLL values.
[andreas@pm8600 ~]$ cat /proc/sys/kernel/l2cr
0xb9000068:  enabled, no parity, 1MB, +2 clock, pipelined burst SRAM, 
copy-back, 0.5ns hold

So if you want to try, you could do
'echo '0xb9000000' > /proc/sys/kernel/l2cr' BUT as said, it could freeze 
your box!! I'd try it first in OS9.
For a coding of the L2 value see the moto or ibm 750 cpu pdf.
Or in short below.

Andreas

AGAIN: Be carefully what you do, ask twice!! Even me;-)

example:
0xbd008000:	enabled, no parity, 1MB, +3 clock, pipelined burst SRAM, 
copy-back,
			0.5ns hold, DLL slow
0		L2E	1	/* enabled */
1		L2PE	0	/* no parity */
2-3		L2SIZ	11	/* 1 Mbyte */
4-6		L2CLK	110	/* 3 */
7-8		L2RAM	10	/* Pipelined (register-register) synchronous burst SRAMs */
9		L2DO	0	/* data-only */
10		L2I	0	/* global invalidate */
11		L2CTL	0	/* RAM control (ZZ enable) */
12		L2WT	0	/* copy-back */
13		L2TS	0	/* test support */
14-15		L2OH	0	/* output hold 0.5 nS */
16		L2SL	1	/* DLL slow */
17		L2DF	0	/* differential clock */
18		L2BYP	0	/* DLL bypass */
19-30	-		0	/* reserved */
31		L2IP	0	/* global invalidate in progress (read only) */